Field of Invention
The present invention relates generally to a gain circuit of power sourcing equipment, and more particularly to a gain circuit for power sourcing equipment of Power over Ethernet with high gain precision.
Related Art
Power over Ethernet (PoE) has found widespread application in many areas. For example, IEEE has released two standards that relate to PoE—IEEE 802.3af-2003 and IEEE 802.3at-2009. PoE technology allows supplying electric power through Ethernet to devices such as Internet phone, wireless base stations, network cameras, hubs, and even computers Without the need of extra power socket. Combining data transmission and power supply, PoE technology can reduce the cost and complexity of the overall network computing system.
FIG. 1 illustrates a circuit diagram of a gain circuit for a conventional power sourcing equipment of PoE. As shown, the gain circuit includes a power transistor 51 for providing a return current path for a powered device 50. For example, from the terminal PortP, 7.5 mA of the current IDC_dis may pass through the powered device 50, and to the terminal PortN. In FIG. 1, the output ports consist of the output signal on terminal PortP and return signal on terminal PortN. The return signal on terminal PortN is inputted through the power transistor 51, and converted into a voltage Vrs by the resistor Rsense. The voltage Vrs is then supplied to the positive terminal VP of the operational amplifier OP1 of the gain circuit 10.
The gain circuit 10 in FIG. 1 is adapted to receive the current from the powered device 50 and convert it into a voltage through the resistor Rsense. It then amplifies the voltage to provide a stable voltage Vout to electronic devices (not shown) connected to the PoE system. The gain circuit 10 in FIG. 1 includes the operational amplifier OP1, and resistors R1 and R2 connected in series and to the operational amplifier OP1. The positive terminal VP of the operational amplifier OP1 receives a voltage Vrs from the power transistor 51. The negative terminal VN of the operational amplifier OP1 is connected to the output terminal of the operational amplifier OP1 through the resistor R2. VDDA is a positive power source, and GND is ground, which operates as the negative power source.
The ideal gain function of the gain circuit 10 in FIG. 1 is represented as follows.Vout=(Vrs)*(R2+R1)/R1
However, in a real operational amplifier, the gain function is not as ideal. FIG. 2 illustrates a circuit diagram of the operational amplifier OP1. As shown, the input transistors M1 and M2 may be a matching pair with the same dimensions (length and width). However, variations during the manufacturing process of the devices may result in device mismatches and cause an offset voltage Vos. Vos=VP−VN. This offset voltage between the positive terminal and the negative terminal of the operational amplifier OP1 is about ±(0˜10 mV), and is an inherent, non-ideal characteristic of the operational amplifier.
In such a circumstance, the gain function of the operational amplifier OP1 is represented as below.Vout=(Vrs+Vos)*(R2+R1)/R1
Vos is the input offset voltage, and it varies in accordance with the manufacturing process; thereby resulting in a nonlinear factor to the output voltage Vout and causing a poor precision of the voltage gain. In addition, under some conditions, the voltage gain deviation may be so great that it cannot be compensated. For example, when the current IDC_dis of the powered device 50 is 7.5 mA, the output voltage Vrs of the power transistor 51 will be:Vrs=IDC_dis*Rsense=7.5 mA*0.50Ω=3.75 mV
If the deviation tolerance of the input offset voltage Vos is between 3.75 mV and 10 mV, since Vrs is just 3.75 mV, this may result in 100% error to the output voltage Vout of the gain circuit 10. This shows that the gain circuit in FIG. 1 is not suitable for the Power over Ethernet application.
FIG. 3 illustrates another circuit diagram of a gain circuit for a power sourcing equipment of PoE. The gain circuit in FIG. 3 improves on the one in FIG. 1 by trying to eliminate the input offset voltage Vos. FIG. 3 applies the same reference numerals to the elements as they are used in FIG. 1. The gain circuit of FIG. 3 may be referred to in P. E. Allen, Lecture 390—Open-Loop Comparators (Reading: AH-461-475), ECE 6412—Analog Integrated Circuit Design—II, Georgia Institute of Technology, USA, 2002.
The gain circuit 10 of FIG. 3 includes the operational amplifier OP1, and the resistors R1 and R2. It further includes a capacitor Cos and a clock circuit Ck. The capacitor Cos is connected between the negative terminal VN of the operational amplifier OP1 and the resistor R2. The connection status of the capacitor Cos with respect to the other elements is controlled by switches. FIG. 4 illustrates the clock signal of the clock circuit. When the clock signal is High, the Ck switches are closed and the CkB switch is opened. This causes the capacitor Cos to store the voltage Vos. When the clock signal is Low, the CkB switch is closed and the Ck switches are opened. This causes capacitor Cos to be connected to the resistor R2 in series.
In a real application, the input offset voltage. Vos is about ±(0˜10 mV). The capacitor Cos can store the voltage Vcos when the clock signal is High. When the clock signal is Low, the stored voltage Vcos is deducted from (Vrs+Vos). In theory, the value of Vcos is equal to the input offset voltage Vos. Therefore, when the clock signal is Low, the input offset voltage Vos will not affect the gain factor. Specifically, the gain function of the operational amplifier OP1 can be represented as:Vout=(Vrs+Vos−Vcos)*(R2+R1)/R1=Vrs*(R1+R2)/R1
Because Vos=Vcos, Vos is removed from the gain function, and this improves the gain accuracy. However, the gain circuit 10 may not be able to function properly when the current IDC_dis from the powered device 50 is 7.5 mA.
As previously explained, Vrs=IDC_dis*Rsense=7.5 mA*0.5Ω=3.75 mV. Therefore, when the clock signal is High, and assumes VN=−10 mV, the input offset voltage Vos should be:Vos=VP−VN=3.75 mV−(VN)=3.75 mV−(−10 mV)=13.75 mV
However, because the negative terminal VN of the operational amplifier OP1 is connected to the ground via the resistor R1, the minimum voltage it can achieve is only 0V. The actual value of Vcos becomes:Vcos=VP−VN=3.75 mV−(−0V)=3.75 mV
In other words, since the value of VN is limited to 0V, the maximum voltage stored in the capacitor Cos is capped at 3.75 mV, which may not be the actual value of the voltage Vos. Namely, when the value of Vos is between −3.75 mV and −10 mV, even if we are able to deduct the voltage Vcos stored in the capacitor Cos, the effect of the Vos to the output voltage Vout is still not eliminated. Moreover, when the input offset voltage Vos is less than −7.5 mV, the deviation of the gain can still be 100% and cannot be compensated accordingly. Thus, the gain circuit in FIG. 3 is also not suitable for Power over Ethernet applications.
Accordingly, there exists a need for a gain circuit with high gain precision for power sourcing equipment of Power over Ethernet, and with more tolerability towards manufacturing process. The present invention addresses these needs.